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ltc4360-1/ltc4360-2 1 436012fa typical application description overvoltage protection controller the ltc ? 4360 overvoltage protection controller safeguards 2.5v to 5.5v systems from power supply overvoltage. it is designed for portable devices with multiple power supply options including wall adaptors, car battery adaptors and usb ports. the ltc4360 controls an external n-channel mosfet in series with the input power supply. during overvoltage transients, the ltc4360 turns off the mosfet within 1s, isolating downstream components from the input supply. inductive cable transients are absorbed by the mosfet and load capacitance. in most applications, the ltc4360 provides protection from transients up to 80v without requiring transient voltage suppressors or other external components. the ltc4360 has a delayed start-up and an adjustable dv/dt ramp-up for inrush current limiting. a pwrgd pin provides power good monitoring for v in . following an overvolt - age condition, the ltc4360 automatically restarts with a start-up delay. the ltc4360-1 features a soft shutdown controlled by the on pin, while the ltc4360-2 controls an optional external p-channel mosfet for negative voltage protection. output protected from overvoltage at input features applications n 2.5v to 5.5v operation n overvoltage protection up to 80v n no input capacitor or tvs required for most applications n 2% accurate 5.8v overvoltage threshold n <1s overvoltage turn-off, gentle shutdown n controls n-channel mosfet n adjustable power-up dv/dt limits inrush n reverse voltage protection (ltc4360-2) n power good output n low current shutdown (ltc4360-1) n available in a tiny 8-lead sc70 package n usb protection n handheld computers n cell/smart phones n mp3/mp4 players n digital cameras gate si1470dh in 436012 ta01a v out 5v 1.5a v in 5v ltc4360-1 on out pwrgd gnd c out protection from overvoltage v gate 10v/div v in , v out 5v/div 0.5s/div 436012 ta01b si1470dh c out = 10f v out v in l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot, powerpath, how swap and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4360-1/ltc4360-2 2 436012fa bias supply voltage (in) ............................ C0.3v to 85v input voltages out, on ................................................... C0.3v to 9v output voltages pwrgd .................................................... C0.3v to 9v gate (note 3) ........................................ C0.3v to 15v gatep .................................................... C0.3v to 85v in to gatep ........................................... C0.3v to 10v (notes 1, 2) order information lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc4360csc8-1#trmpbf ltc4360csc8-1#trpbf ldxn 8-lead plastic sc70 0c to 70c ltc4360csc8-2#trmpbf ltc4360csc8-2#trpbf ldxp 8-lead plastic sc70 0c to 70c ltc4360isc8-1#trmpbf ltc4360isc8-1#trpbf ldxn 8-lead plastic sc70 C40c to 85c ltc4360isc8-2#trmpbf ltc4360isc8-2#trpbf ldxp 8-lead plastic sc70 C40c to 85c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ absolute maximum ratings ltc4360-1 ltc4360-2 in 1 gnd 2 gnd 3 gnd 4 8 gate 7 out 6 on 5 pwrgd top view sc8 package 8-lead plastic sc70 t jmax = 125c, ja = 270c/w in 1 gnd 2 gnd 3 gnd 4 8 gatep 7 gate 6 out 5 pwrgd top view sc8 package 8-lead plastic sc70 t jmax = 125c, ja = 270c/w pin configuration operating temperature range ltc4360c ................................................ 0c to 70c ltc4360i ............................................. C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c
ltc4360-1/ltc4360-2 3 436012fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v on = 0v (ltc4360-1) unless otherwise noted. symbol parameter conditions min typ max units supplies v in input voltage range l 2.5 80 v v in(uvl) input undervoltage lockout v in rising l 1.8 2.1 2.45 v i in input supply current ltc4360-1 v on = 0v, ltc4360-2 l 220 400 a ltc4360-1 v on = 2.5v l 1.5 10 a thresholds v in(ov) in pin overvoltage threshold v in rising l 5.684 5.8 5.916 v ?v ov overvoltage hysteresis l 25 100 200 mv external gate drive ?v gate external n-channel mosfet gate drive (v gate C v out ) 2.5v v in < 3v, i gate = C1a 3v v in < 5.5v, i gate = C1a l l 3.5 4.5 4.5 6 6 7.9 v v v gate(th) gate high threshold for pwrgd status v in = 3.3v v in = 5v l l 5.7 6.7 6.3 7.2 6.8 7.8 v v i gate(up) gate pull-up current v gate = 1v l C5 C10 C15 a v gate(up) gate ramp-up v gate = 1v to 7v l 1.5 3 4.5 v/ms i gate(fst) gate fast pull-down current fast turn-off, v in = 6v, v gate = 9v l 15 30 60 ma i gate(dn) gate pull-down current v on = 2.5v, v gate = 9v (ltc4360-1) l 10 40 80 a input pins i out(in) out input current v out = 5v, v on = 0v v out = 5v, v on = 2.5v l l 5 10 0 20 3 a a v on (th) on input threshold (ltc4360-1) l 0.4 1.5 v i on on pull-down current v on = 2.5v (ltc4360-1) l 2.5 5 10 a output pins v gatep(clp) in to gatep clamp voltage v in = 8v to 80v (ltc4360-2) l 5 5.8 7.5 v r gatep gatep resistive pull-down v gatep = 3v (ltc4360-2) l 0.8 2 3.2 m v pwrgd (ol) pwrgd output low voltage v in = 5v, i pwrgd = 3ma l 0.23 0.4 v r pwrgd pwrgd pull-up resistance to out v in = 6.5v, v pwrgd = 1v l 250 500 800 k delay t on gate on delay v in high to i gate = C5a l 50 130 200 ms t off gate off propagation delay v in = step 5v to 6.5v to pwrgd high l 0.25 1 s t pwrgd pwrgd delay v in = step 5v to 6.5v v gate > v gate(th) to pwrgd low l l 25 0.25 65 1 100 s ms t on (off) on high to gate off v on = step 0v to 2.5v (ltc4360-1) l 2 5 s note 3: an internal clamp limits v gate to a minimum of 4.5v above v out . driving this pin to voltages beyond this clamp may damage the device.
ltc4360-1/ltc4360-2 4 436012fa typical performance characteristics pwr gd voltage vs pwr gd current gate off propagation delay vs overdrive (v ovdrv ) normal start-up sequence gate slow ramp-up entering sleep mode (ltc4360-1) input supply current vs input voltage gate drive vs gate current gate fast pull-down current vs temperature v in 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 20ms/div 436012 g07 figure 5 circuit r in = 150m, l in = 0.7h load = 10, c out = 10f v in 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 1ms/div 436012 g08 figure 5 circuit r in = 150m, l in = 0.7h load = 10, c out = 10f v on 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 50s/div 436012 g09 figure 5 circuit r in = 150m, l in = 0.7h load = 10, c out = 10f v in (v) 1 0.1 i in (a) 1 10 100 1000 10 436012 g01 100 v on = 2.5v (ltc4360-1) ltc4360-1 v on = 0v, ltc4360-2) i gate (a) v in = 5v v in = 3v v in = 2.5v 0 0 ?v gate (v) 1 2 3 7 6 5 4 8 2 4 6 8 436012 g02 10 12 temperature (c) ?50 20 i gate(fst) (ma) 25 30 35 40 ?25 0 25 50 436012 g03 75 v in = 6v v gate = 9v 100 i pwrgd (ma) 0 0 v pwrgd(ol) (mv) 200 100 300 400 500 1 2 3 4 436012 g04 5 t a = 25c, v in = 5v, v on = 0v (ltc4360-1) unless otherwise noted. gate voltage and gate high threshold (for pwr gd status) vs input voltage v in (v) 2.5 4 v gate / v gate(th) (v) 5 10 9 8 7 6 11 12 3.5 3 4 4.5 5 5.5 436012 g06 6 v in = v out v gate v gate(th) v ovdrv (v) 0 0 t off (s) 1 6 5 4 3 2 7 8 0.5 1 1.5 2 436012 g05 2.5 v in = step 5v to (v in(ov) + v ovdrv )
ltc4360-1/ltc4360-2 5 436012fa pin functions gate: gate drive for external n-channel mosfet. an internal charge pump provides a 10a pull-up current to charge the gate of the external n-channel mosfet. an additional ramp circuit limits the gate ramp rate when turning on to 3v/ms. for slower ramp rates, connect an external capacitor from gate to gnd. an internal clamp limits gate to 6v above the out pin voltage. an internal gate high comparator controls the pwrgd pin. gatep (ltc4360-2): gate drive for external p-channel mosfet. gatep connects to the gate of an optional external p-channel mosfet to protect against negative voltages at in. this pin is internally clamped to 5.8v below v in . an internal 2m resistor connects this pin to ground. connect to in if not used. gnd: device ground. in: supply voltage input. connect this pin to the input power supply. this pin has an overvoltage threshold of 5.8v. after an overvoltage event, this pin must fall below v in(ov) C ?v ov to release the overvoltage lockout. dur - ing lockout, gate is held low and the pwrgd pull-down releases. on (ltc4360-1): on control input. a logic low at on enables the ltc4360-1. a logic high at on activates a low current pull-down at the gate pin and causes the ltc4360-1 to enter a low current sleep mode. an internal 5a current pulls on down to ground. connect to ground or leave open if unused. out: output voltage sense input for gate clamp. connect to the source of the external n-channel mosfet to sense the output voltage for gate to out clamp. pwr gd : power good status. open-drain output with internal 500k resistive pull-up to out. pulls low 65ms after gate ramps above v gate(th) . block diagram ? + 5.8v 5.7v gnd 436012 bd 10a in 5a 1v on (ltc4360-1) out pwrgd 5.8v v gate(th) 500k 1.8m 200k 5.8v gatep (ltc4360-2) gate control charge pump overvoltage comparator gate high comparator + ? + ?
ltc4360-1/ltc4360-2 6 436012fa operation mobile devices like cell phones and mp3/mp4 players have highly integrated subsystems fabricated from deep submi - cron cmos processes. the small form factor is accompanied by low absolute maximum voltage ratings. the sensitive electronics are susceptible to damage from transient or dc overvoltage conditions from the power supply. failures or faults in the power adaptor can cause an over - voltage event. so can hot-plugging an ac adaptor into the power input of the mobile device (see ltc application note 88). todays mobile devices derive their power supply or recharge their internal batteries from multiple alternative inputs like ac wall adaptors, car battery adaptors and usb ports. a user may unknowingly plug in the wrong adaptor, damaging the device with a high or even a negative power supply voltage. the ltc4360 protects low voltage electronics from these overvoltage conditions by controlling a low cost external n- channel mosfet configured as a pass transistor. at power-up (v in > 2.1v), a start-up delay cycle begins. any overvoltage condition causes the delay cycle to continue until a safe voltage is present. when the delay cycle com - pletes, an internal high side switch driver slowly ramps up the mosfet gate, powering up the output at a controlled rate and limiting the inrush current to the output capacitor. if the voltage at the in pin exceeds 5.8v (v in(ov) ), gate is pulled low quickly to protect the load. the incoming power supply must remain below 5.7v (v in(ov) C ?v ov ) for the duration of the start-up delay to restart the gate ramp-up. the ltc4360-1 has a cmos compatible on input. when driven low, the part is enabled. when driven high, the external n-channel mosfet is turned off and the supply current of the ltc4360-1 drops to 1.5a. the pwrgd pull-down releases during this low current sleep mode, uvlo or overvoltage and the subsequent 130ms start-up delay. after the start-up delay, gate starts its slow ramp- up and ramps higher than v gate(th) to trigger a 65ms delay cycle. when that completes, pwrgd pulls low. the ltc4360-2 has a gatep pin that drives an optional external p-channel mosfet to provide protection against negative voltages at in. the typical ltc4360 application protects 2.5v to 5.5v sys - tems in portable devices from power supply overvoltage. the basic application circuit is shown in figure 1. device operation and external component selection is discussed in detail in the following sections. applications information gate c out 10f m1 si1470dh in 436012 f01 v out 5v 1.5a v in 5v ltc4360-1 on out pwrgd gnd figure 1. protection from input overvoltage start-up when v in is less than the undervoltage lockout level of 2.1v, the gate driver is held low and the pwrgd pull- down is high impedance. when v in rises above 2.1v and on (ltc4360-1) is held low, a 130ms delay cycle starts. any undervoltage or overvoltage event at in (v in < 2.1v or v in > 5.7v) restarts the delay cycle. this delay allows the n-channel mosfet to isolate the output from any input transients that occur at start-up. when the delay cycle completes, gate starts its slow ramp-up. gate control an internal charge pump provides a gate overdrive greater than 3.5v when 2.5v v in < 3v. if v in 3v, the gate drive is guaranteed to be greater than 4.5v. this allows the use of logic-level n-channel mosfets. an internal 6v clamp between gate and out protects the mosfet gate.
ltc4360-1/ltc4360-2 7 436012fa figure 2 details pwrgd behavior for a ltc4360-1 with 1k pull-up to 5v at pwrgd . applications information the gate ramp rate is limited to 3v/ms. v out follows at a similar rate which results in an inrush current into the load capacitor c out of: i i n r u s h = c o u t ? dv g a t e dt = c o u t ? 3 m a / f [ ] the servo loop is compensated by the parasitic capaci - tance of the external mosfet. no further compensation components are normally required. in the case where the parasitic capacitance is less than 100pf, a 100pf compensa - tion capacitor between gate and ground may be required. an even slower gate ramp and lower inrush current can be achieved by connecting an external capacitor, c g , from gate to ground. the voltage at gate then ramps up with a slope equal to 10a/c g [v/s]. choose c g using the formula: c g = 10 a i i n r u s h ? c o u t overvoltage when power is first applied, v in must remain below 5.7v (v in(ov) C ?v ov ) for more than 130ms before gate is ramped up to turn on the mosfet. if v in then rises above 5.8v (v in(ov) ), the overvoltage comparator activates the 30ma fast pull-down on gate within 1s. after an over - voltage condition, the mosfet is held off until v in once again remains below 5.7v for 130ms. pwrgd output pwrgd is an active low output with a mosfet pull- down to ground and a 500k resistive pull-up to out. the pwrgd pin pull-down releases during the low current sleep mode (invoked by on high), uvlo or overvolt - age and the subsequent 130ms start-up delay. after the start-up delay, gate starts its slow ramp-up and control of the pwrgd pull-down passes on to the gate high comparator. v gate > v gate(th) for more than 65ms asserts the pwrgd pull-down and v gate < v gate(th) releases the pull-down. the pwrgd pull-down is capable of sink - ing up to 3ma of current allowing it to drive an optional led. to interface pwrgd to another i/o rail, connect a resistor from pwrgd to the i/o rail with a resistance low enough to override the internal 500k pull-up to out. figure 2. pwr gd behavior in out gate on pwrgd v gate(th) v gate(th) v in(uvl) v in(ov) ??v ov start-up from uvlo restart from ov ov restart from on on 130ms 65ms 130ms 65ms 130ms 65ms v in(ov) v gate(th) v gate(th) on input (ltc4360-1) on is a cmos compatible, active low enable input. it has a default 5a pull-down to ground. connect this pin to ground or leave open to enable normal device operation. if it is driven high while the external mosfet is turned on, gate is pulled low with a weak pull-down current (40a) to turn off the external mosfet gradually, minimizing input voltage transients. the ltc4360-1 then goes into a low current sleep mode, drawing only 1.5a at in. when on goes back low, the part restarts with a 130ms delay cycle. gatep control (ltc4360-2) gatep has a 2m resistive pull-down to ground and a 5.8v zener clamp in series with a 200k resistor to in. it con - trols the gate of an optional external p-channel mosfet to provide negative voltage protection. the 2m resistive pull-down turns on the mosfet once v in C v gatep is more than the mosfet gate threshold voltage. the in to gatep zener protects the mosfet from gate overvoltage by clamping its v gs to 5.8v when v in goes high.
ltc4360-1/ltc4360-2 8 436012fa figure 3. mosfet configurations gatep supply in overvoltage, reverse current protection negative voltage protection gate overvoltage, reverse current protection gate gate gatep 436012 f03 overvoltage protection overvoltage protection negative voltage protection gate out supply in out supply in out supply in out m1 m1 m3 m1 m2 m1 m2 m3 applications information mosfet configurations and selection t he ltc4360 can be used with various external mosfet configurations (see figure 3). the simplest configuration is a single n-channel mosfet. it has the lowest r ds(on) and voltage drop and is thus the most power efficient solution. when gate is pulled to ground, the mosfet can isolate out from a positive voltage at in up to the bv dss of the mosfet. however, reverse current can still flow from out to in via the parasitic body diode of the mosfet. for near zero reverse leakage current protection when gate is pulled to ground, back-to-back n-channel mosfets can be used. adding an additional p-channel mosfet controlled by gatep (ltc4360-2) provides negative input voltage protection down to the bv dss of the p-channel mosfet. anothe r configuration consists of a p-channel mosfet controlled by gatep and a n-channel mosfet controlled by gate. this provides protection against overvoltage and negative voltage but not reverse current. input transients figure 4 shows a typical set-up when an ac wall adaptor charges a mobile device. the inductor l in represents the lumped equivalent inductance of the cable and the emi filter found in some wall adaptors. r in is the lumped equivalent resistance of the cable, adaptor output capacitor esr and the connector contact resistance.
ltc4360-1/ltc4360-2 9 436012fa applications information l in and r in form an lc tank circuit with any capacitance at in. if the wall adaptor is powered up first, plugging the wall adaptor output to in does the equivalent of applying a voltage step to this lc circuit. the resultant voltage overshoot at in can rise to twice the dc out - figure 4. 20v hot-plug into a 10f capacitor + load 436012 f04a mobile device wall adaptor ac/dc c out in l in r in cable i cable v in 10v/div i cable 20a/div 5s/div 436012 f04b r in = 150m, l in = 0.7h load = 10, c out = 10f put voltage of the wall adaptor as shown in figure 4. figure 5 shows the 20v adaptor output applied to the ltc4360. due to the low capacitance at the in pin, the plug-in transient has been brought down to a manage - able level. figure 5. 20v hot-plug into the ltc4360 + load ltc4360 m1 si1470dh gnd gate 436012 f04a mobile device wall adaptor ac/dc c out in out l in r in cable i cable in out v in 10v/div v out 1v/div i cable 20a/div 5s/div 436012 f04b r in = 150m, l in = 0.7h load = 10, c out = 10f
ltc4360-1/ltc4360-2 10 436012fa figure 8. set-up for testing 20v plugged into 5v system load 436012 f07 out c out m1 si1470dh in l in r in 20v wall adapter 5v usb ltc4360 in r1 100k d1 b160 out gnd gate + ? + ? i cable applications information figure 7. input transient after overvoltage v adaptor /v out 5v/div v in 20v/div i cable 5a/div 2s/div 436012 f06 figure 5 circuit r in = 150, l in = 2h load = 10, c out = 10f v adaptor v out as the in pin can withstand up to 80v, a high voltage n- channel mosfet can be used to protect the system against rugged abuse from high transient or dc voltages up to the bv dss of the mosfet. figure 6 shows a 50v input plugged into the ltc4360 controlling a 60v rated mosfet. input transients also occur when the current through the cable inductance changes abruptly. this can happen when the ltc4360 turns off the n-channel mosfet rapidly in an overvoltage event. figure 7 shows the effects of a voltage transient at the wall adaptor output v adaptor . the current in l in will cause v in to overshoot and avalanche the n- channel mosfet to c out . typically, in will be clamped to a voltage of v out + 1.3 ? (bv dss of si1470dh) = 45v. this is well below the 85v absolute maximum voltage rating of the ltc4360. the single, nonrepetitive, pulse of energy (e as ) absorbed by the mosfet during this avalanche breakdown with a peak current i as is approximated by the formula: e as = 0.5 ? l in ? i as 2 for l in = 2h and i as = 4a, then e as = 16j. this is within the i as and e as capabilities of most mosfets including the si1470dh. so in most instances, the ltc4360 can ride through such transients without a bypass capacitor, transient voltage suppressor or other external components at in. figure 8 shows a particularly severe situation which can occur in a mobile device with dual power inputs. a 20v wall adaptor is mistakenly hot-plugged into the 5v device figure 6. 50v hot-plug into the ltc4360 v in 20v/div v out 1v/div i cable 5a/div 5s/div 436012 f05 fdc5612 r in = 150m, l in = 0.7h load = 10, c out = 10f
ltc4360-1/ltc4360-2 11 436012fa applications information figure 10. recommended layout for n-channel mosfet and p-/n-channel mosfet configurations ltc4360 to shut off the mosfet before v out overshoots to a dangerous voltage. a larger c out also helps to lower the ?v out due to the discharge of the energy in l in if the mosfet bv dss is used as an input clamp. layout considerations figure 10 shows example pcb layouts for the single n-channel mosfet (sc70 package) configuration and the p-channel mosfet/n-channel mosfet (complementary p, n mosfet in tsop-6 package) configuration. keep the traces to the mosfets wide and short. the pcb traces associated with the power path through the mosfets should have low resistance. si3590dv 436012 f09 si1470dh supply/in supply in out out gnd gnd 6 5 4 1 2 3 1 2 3 4 8 7 6 5 ltc4360-2 1 2 3 4 8 7 6 5 1 2 3 6 5 4 ltc4360-1 figure 9. overvoltage protection waveforms when 20v plugged into 5v system v in 20v/div v gate 10v/div v out 5v/div i cable 10a/div 1s/div 436012 f08 figure 8 circuit r in = 150m, l in = 2h load = 10, c out = 10f (16v, size 1210) with the usb input already live. as shown in figure 9, a large current can build up in l in to charge up c out . when the n-channel mosfet shuts off, the energy stored in l in is dumped into c out , causing a large 40v input transient . the ltc4360 limits this to a 1v rise in the output voltage. if the voltage rise at v out due to the discharge of the energy in l in into c out is not acceptable or the avalanche capability of the mosfet is exceeded, an additional exter - nal clamp such as the smaj24a can be placed between in and gnd. c out is the decoupling capacitor of the protected circuits and its value will largely be determined by their requirements. using a larger c out will work with l in to slow down the dv/dt at out, allowing time for the
ltc4360-1/ltc4360-2 12 436012fa package description sc8 package 8-lead plastic sc70 (reference ltc dwg # 05-08-1639 rev ?) 1.15 ? 1.35 (note 4) 1.80 ? 2.40 0.15 ? 0.27 8 plcs (note 3) sc8 sc70 0905 rev ? 1.80 ? 2.20 (note 4) 0.50 bsc pin 1 pin 8 0.80 ? 1.00 1.00 max 0.00 ? 0.10 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. details of the pin 1 identifier are optional, but must be located within the index area 7. eiaj package reference is eiaj sc-70 and jedec mo-203 variation ba 2.8 bsc 0.30 max 0.50 ref recommended solder pad layout per ipc calculator 1.8 ref 1.00 ref index area (note 6) 0.10 ? 0.18 (note 3) 0.26 ? 0.46 gauge plane 0.15 bsc 0.10 ? 0.40
ltc4360-1/ltc4360-2 13 436012fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 01/11 revised features 1 revised conditions for v gatep(clp) and t off in electrical characteristics section 3 revised gate control in applications information section 6
ltc4360-1/ltc4360-2 14 436012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0111 rev a ? printed in usa related parts typical application 5v system protected from 24v power supplies gate v io 5v c out 10f r1 1k d1 ln1351ctr si3590dv m2 m1 in 436012 ta02 v out 5v 0.5a v in 5v ltc4360-2 gatep out pwrgd gnd part number description comments ltc2935 ultralow power supervisor with eight pin-selectable thresholds 500na quiescent current, 2mm 2mm 8-lead dfn and tsot-23 packages lt3008 20ma, 45v, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 2.0v to 45v, v out = 0.6v to 39.5v; thinsot? and 2mm 2mm dfn-6 packages lt3009 20ma, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 1.6v to 20v, v out = 0.6v to 19.5v; thinsot and sc-70 packages ltc3576/ ltc3576-1 switching usb power manager with usb otg + triple step-down dc/dcs complete multifunction pmic: bi-directional switching power manager + 3 bucks + ldo ltc4090/ ltc4090-5 high voltage usb power manager with ideal diode controller and high efficiency li-ion battery charger high efficiency 1.2a charger from 6v to 38v (60v max) input charges single cell li-ion batteries directly from a usb port ltc4098 usb-compatible switchmode power manager with ovp high v in : 38v operating, 60v transient; 66v ovp. 1.5a max charge current from wall, 600ma charge current from usb ltc4210 single channel, low voltage hot swap? controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4213 no r sense ? electronic circuit breaker controls load voltages from 0v to 6v. 3 selectable circuit breaker thresholds. dual level overcurrent fault protection lt4356 surge stopper overvoltage/overcurrent protection regulator wide operation range: 4v to 80v. reverse input protection to C60v. adjustable output clamp voltage ltc4411 sot-23 ideal diode 2.6a forward current, 28mv regulated forward voltage ltc4412 2.5v to 28v, low loss powerpath? controller in thinsot more efficient than diode-oring, automatic switching between dc sources, simplified load sharing ltc4413-1/ ltc4413-2 dual 2.6a, 2.5v to 5.5v fast ideal diodes in 3mm 3mm dfn 130m on resistance, low reverse leakage current, 18mv regulated forward voltage (ltc4413-2 with overvoltage protection sensor) 5v system protected from 24v power supplies and reverse current v io 5v c out 10f r1 1k d1 ln1351ctr m2 si1471dh m1 m3 fdc6561an 436012 ta03 v out 5v 0.5a v in 5v gate in ltc4360-2 gatep out pwrgd gnd

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